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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD8400/ad8402/ad8403 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www. analog.com fax: 781/326-8703 ? analog devices, inc., 2002 1-/2-/4-channel digital potentiometers functional block diagram 8 8-bit latch ck rs 8 8-bit latch ck rs 8 8-bit latch ck rs 8 8-bit latch ck rs shdn dac select a1, a0 1 10-bit serial latch ck q rs d rs sdo ad8403 v dd dgnd sdi clk cs 8 2 3 2 4 rdac1 shdn w1 a1 b1 agnd1 rdac2 shdn w2 a2 b2 agnd2 rdac3 shdn w3 a3 b3 agnd3 rdac4 shdn w4 a4 b4 agnd4 features 256-position replaces 1, 2, or 4 potentiometers 1 k , 10 k , 50 k , 100 k power shutdownless than 5 a 3-wire spi-compatible serial data input 10 mhz update data loading rate 2.7 v to 5.5 v single-supply operation midscale preset applications mechanical potentiometer replacement programmable filters, delays, time constants volume control, panning line impedance matching power supply adjustment general description the AD8400/ad8402/ad8403 provide a single, dual or quad channel, 256 position digitally controlled variable resistor (vr) device. these devices perform the same electronic adjustment function as a potentiometer or variable resistor. the AD8400 contains a single variable resistor in the compact so-8 package. the ad8402 con tains two independent variable resistors in space-saving so-14 surface- mount packages. the ad8403 contains four independent variable resistors in 24-lead pdip, soic, and tssop packages. each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input register. the resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the vr latch. each variable resistor offers a completely programmable value of resistance, between the a terminal and the wiper or the b terminal and the wiper. the fixed a to b terminal resistance of 1 k ? , 10 k ? , 50 k ? , or 100 k ? has a 1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/ c. a unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs avoiding any make-before-break or break-before-make operation. each vr has its own vr latch that holds its programmed resistance value. these vr latches are updated from an spi compatible serial- to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. ten data bits make up the data word clocked into the serial input register. the data word is decoded where the first two bits determine the address of the vr latch to be loaded, the last eight bits are data. a serial data output pin at the opposite end of the serial register allows simple daisy-chaining in multiple vr applications without additional external decoding logic. the reset ( rs ) pin forces the wiper to the midscale position by loading 80 h into the vr latch. the shdn pin forces the resistor to an end-to-end open circuit condition on the a terminal and shorts the wiper to the b terminal, achieving a microwatt power shutdown state. when shdn is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown. the digital interface is still active in shutdown so that code changes can be made that will produce new wiper positions when the device is taken out of shutdown. the AD8400 is available in both the so-8 surface-mount and the 8-lead plastic dip package. the ad8402 is available in both surface mount (so-14) and 14-lead plastic dip packages, while the ad8403 is available in a narrow body 24-lead plastic dip and a 24-lead surface-mount package. the ad8402/ad8403 are also offered in the 1.1 mm thin tssop-14/tssop-24 packages for pcmcia applications. all parts are guaranteed to operate over the extended industrial tem- perature range of ?0 c to +125 c. code C decimal 100 75 50 25 0 0 6 4 128 192 255 r wa (d), r wb (d) C % of nominal r ab r wa r wb figure 1. rwa and rwb vs. code
rev. c C2C AD8400/ad8402/ad8403?pecifications (v dd = 3 v 10% or 5 v 10%, v a = v dd , v b = 0 v, ?0 c t a +125 c unless otherwise noted.) electrical characteristics?0 k version parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode (specifications apply to all vrs) resistor differential nl 2 r-dnl r wb , v a = no connect ? 1/4 +1 lsb resistor nonlinearity 2 r-inl r wb , v a = no connect ? 1/2 +2 lsb nominal resistance 3 r ab t a = 25 c, model: ad840xyy10 8 10 12 k ? resistance tempco ? r ab / ? tv ab = v dd , wiper = no connect 500 ppm/ c wiper resistance r w i w = 1 v/r 50 100 ? nominal resistance match ? r/r ab ch 1 to 2, 3, or 4, v ab = v dd , t a = 25 c 0.2 1 % dc characteristics potentiometer divider specifications apply to all vrs resolution n 8 bits integral nonlinearity 4 inl ? 1/2 +2 lsb differential nonlinearity 4 dnl v dd = 5 v 1 1/4 +1 lsb dnl v dd = 3 v t a = 25 c1 1/4 +1 lsb dnl v dd = 3 v t a = ?0 c, +85 c ?.5 1/2 +1.5 lsb voltage divider tempco ? v w / ? t code = 80 h 15 ppm/ c full-scale error v wfse code = ff h ? ?.8 0 lsb zero-scale error v wzse code = 00 h 0 1.3 2 lsb resistor terminals voltage range 5 v a, b, w 0v dd v capacitance 6 ax, bx c a, b f = 1 mhz, measured to gnd, code = 80 h 75 pf capacitance 6 wx c w f = 1 mhz, measured to gnd, code = 80 h 120 pf shutdown current 7 i a_sd v a = v dd , v b = 0 v, shdn = 0 0.01 5 a shutdown wiper resistance r w_sd v a = v dd , v b = 0 v, shdn = 0, v dd = 5 v 100 200 ? digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v output logic high v oh r l = 2.2 k ? to v dd v dd ?0.1 v output logic low v ol i ol = 1.6 ma, v dd = 5 v 0.4 v input current i il v in = 0 v or +5 v, v dd = 5 v 1 a input capacitance 6 c il 5pf power supplies power supply range v dd range 2.7 5.5 v supply current (cmos) i dd v ih = v dd or v il = 0 v 0.01 5 a supply current (ttl) 8 i dd v ih = 2.4 v or 0.8 v, v dd = 5.5 v 0.9 4 ma power dissipation (cmos) 9 p diss v ih = v dd or v il = 0 v, v dd = 5.5 v 27.5 w power supply sensitivity pss v dd = 5 v 10% 0.0002 0.001 %/% pss v dd = 3 v 10% 0.006 0.03 %/% dynamic characteristics 6, 10 bandwidth ? db bw_10k r = 10 k ? 600 khz total harmonic distortion thd w v a = 1 v rms + 2 v dc, v b = 2 v dc, f = 1 khz 0.003 % v w settling time t s v a = v dd , v b = 0 v, 1% error band 2 s resistor noise voltage e nwb r wb = 5 k ? , f = 1 khz, rs = 0 9 nv/ hz crosstalk 11 c t v a = v dd , v b = 0 v ?5 db notes 1 1 typicals represent average readings at 25 c and v dd = 5 v. 1 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper 1 positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. see tpc 29 test circuit. 1 i w = 50 a for v dd = 3 v and i w = 400 a for v dd = 5 v for the 10 k ? versions. 1 3 v ab = v dd , wiper (v w ) = no connect. 1 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. 1 dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. see tpc 28 test circuit. 1 5 resistor terminals a, b, w have no limitations on polarity with respect to each other. 1 6 guaranteed by design and not subject to production test. resistor-terminal capacitance tests are measured with 2.5 v bias on th e measured terminal. the remaining 1 resistor terminals are left open circuit. 1 7 measured at the ax terminals. all ax terminals are open circuited in shutdown mode. 1 8 worst-case supply current consumed when input logic level at 2.4 v, standard characteristic of cmos logic. see tpc 20 for a plot of i dd versus logic voltage. 1 9 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = 5 v. 11 measured at a v w pin where an adjacent v w pin is making a full-scale voltage change. specifications subject to change without notice.
rev. c C3C AD8400/ad8402/ad8403 specifications (v dd = 3 v 10% or 5 v 10%, v a = v dd , v b = 0 v, ?0 c t a +125 c unless otherwise noted.) parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode (specifications apply to all vrs) resistor differential nl 2 r-dnl r wb , v a = no connect ? 1/4 +1 lsb resistor nonlinearity 2 r-inl r wb , v a = no connect ? 1/2 +2 lsb nominal resistance 3 r ab t a = 25 c, model: ad840xyy50 35 50 65 k ? r ab t a = 25 c, model: ad840xyy100 70 100 130 k ? resistance tempco ? r ab / ? tv ab = v dd , wiper = no connect 500 ppm/ c wiper resistance r w i w = 1 v/r 53 100 ? nominal resistance match ? r/r ab ch 1 to 2, 3, or 4, v ab = v dd , t a = 25 c 0.2 1 % dc characteristics potentiometer divider (specifications apply to all vrs) resolution n 8 bits integral nonlinearity 4 inl ? 1 +4 lsb differential nonlinearity 4 dnl v dd = 5 v 1 1/4 +1 lsb dnl v dd = 3 v t a = 25 c1 1/4 +1 lsb dnl v dd = 3 v t a = ?0 c, +85 c ?.5 1/2 +1.5 lsb voltage divider tempco ? v w / ? t code = 80 h 15 ppm/ c full-scale error v wfse code = ff h ? ?.25 0 lsb zero-scale error v wzse code = 00 h 0 +0.1 +1 lsb resistor terminals voltage range 5 v a, b, w 0v dd v capacitance 6 ax, bx c a, b f = 1 mhz, measured to gnd, code = 80 h 15 pf capacitance 6 wx c w f = 1 mhz, measured to gnd, code = 80 h 80 pf shutdown current 7 i a_sd v a = v dd , v b = 0 v, shdn = 0 0.01 5 a shutdown wiper resistance r w_sd v a = v dd , v b = 0 v, shdn = 0, v dd = 5 v 100 200 ? digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v output logic high v oh r l = 2.2 k ? to v dd v dd ?0.1 v output logic low v ol i ol = 1.6 ma, v dd = 5 v 0.4 v input current i il v in = 0 v or 5 v, v dd = 5 v 1 a input capacitance 6 c il 5pf power supplies power supply range v dd range 2.7 5.5 v supply current (cmos) i dd v ih = v dd or v il = 0 v 0.01 5 a supply current (ttl) 8 i dd v ih = 2.4 v or 0.8 v, v dd = 5.5 v 0.9 4 ma power dissipation (cmos) 9 p diss v ih = v dd or v il = 0 v, v dd = 5.5 v 27.5 w power supply sensitivity pss v dd = 5 v 10% 0.0002 0.001 %/% pss v dd = 3 v 10% 0.006 0.03 %/% dynamic characteristics 6, 10 bandwidth ? db bw_50k r = 50 k ? 125 khz bw_100k r = 100 k ? 71 khz total harmonic distortion thd w v a = 1 v rms + 2 v dc, v b = 2 v dc, f = 1 khz 0.003 % v w settling time t s _50k v a = v dd , v b = 0 v, 1% error band 9 s t s _100k v a = v dd , v b = 0 v, 1% error band 18 s resistor noise voltage e nwb _50k r wb = 25 k ? , f = 1 khz, rs = 0 20 nv/ hz e nwb _100k r wb = 50 k ? , f = 1 khz, rs = 0 29 nv/ hz crosstalk 11 c t v a = v dd , v b = 0 v ?5 db notes 1 1 typicals represent average readings at 25 c and v dd = 5 v. 1 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper 1 positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. see tpc 29 test circuit. 1 i w = v dd /r for v dd = 3 v or 5 v for the 50 k ? and 100 k ? versions. 1 3 v ab = v dd , wiper (v w ) = no connect. 1 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. 1 dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. see tpc 28 test circuit. 1 5 resistor terminals a, b, w have no limitations on polarity with respect to each other. 1 6 guaranteed by design and not subject to production test. resistor-terminal capacitance tests are measured with 2.5 v bias on th e measured terminal. the remaining 1 resistor terminals are left open circuit. 1 7 measured at the ax terminals. all ax terminals are open circuited in shutdown mode. 1 8 worst-case supply current consumed when input logic level at 2.4 v, standard characteristic of cmos logic. see tpc 20 for a plot of i dd versus logic voltage. 1 9 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = 5 v. 11 measured at a v w pin where an adjacent v w pin is making a full-scale voltage change. specifications subject to change without notice. electrical characteristics?0 k and 100 k versions
rev. c C4C AD8400/ad8402/ad8403?pecifications (v dd = 3 v 10% or 5 v 10%, v a = v dd , v b = 0 v, ?0 c t a +125 c unless otherwise noted.) parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode specifications apply to all vrs resistor differential nl 2 r-dnl r wb , v a = no connect ? ? +3 lsb resistor nonlinearity 2 r-inl r wb , v a = no connect ? 1.5 +4 lsb nominal resistance 3 r ab t a = 25 c, model: ad840xyy1 0.8 1.2 1.6 k ? resistance tempco ? r ab / ? tv ab = v dd , wiper = no connect 700 ppm/ c wiper resistance r w i w = 1 v/r ab 53 100 ? nominal resistance match ? r/r ab ch 1 to 2, v ab = v dd , t a = 25 c 0.75 2 % dc characteristics potentiometer divider specifications apply to all vrs resolution n 8 bits integral nonlinearity 4 inl ? 2 +6 lsb differential nonlinearity 4 dnl v dd = 5 v 4 ?.5 +2 lsb dnl v dd = 3 v, t a = 25 c 5 2 +5 lsb voltage divider temperature coefficent ? v w / ? t code = 80 h 25 ppm/ c full-scale error v wfse code = ff h ?0 12 0 lsb zero-scale error v wzse code = 00 h 0 6 10 lsb resistor terminals voltage range 5 v a, b, w 0v dd v capacitance 6 ax, bx c a, b f = 1 mhz, measured to gnd, code = 80 h 75 pf capacitance 6 wx c w f = 1 mhz, measured to gnd, code = 80 h 120 pf shutdown supply current 7 i a_sd v a = v dd , v b = 0 v, shdn = 0 0.01 5 a shutdown wiper resistance r w_sd v a = v dd , v b = 0 v, shdn = 0, v dd = 5 v 50 100 ? digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v output logic high v oh r l = 2.2 k ? to v dd v dd ?0.1 v output logic low v ol i ol = 1.6 ma, v dd = 5 v 0.4 v input current i il v in = 0 v or 5 v, v dd = 5 v 1 a input capacitance 6 c il 5pf power supplies power supply range v dd range 2.7 5.5 v supply current (cmos) i dd v ih = v dd or v il = 0 v 0.01 5 a supply current (ttl) 8 i dd v ih = 2.4 v or 0.8 v, v dd = 5.5 v 0.9 4 ma power dissipation (cmos) 9 p diss v ih = v dd or v il = 0 v, v dd = 5.5 v 27.5 w power supply sensitivity pss ? v dd = 5 v 10% 0.0035 0.008 %/% pss ? v dd = 3 v 10% 0.05 0.13 %/% dynamic characteristics 6, 10 bandwidth ? db bw_1k r = 1 k ? 5,000 khz total harmonic distortion thd w v a = 1 v rms + 2 v dc, v b = 2 v dc, f = 1 khz 0.015 % v w settling time t s v a = v dd , v b = 0 v, 1% error band 0.5 s resistor noise voltage e nwb r wb = 500 ? , f = 1 khz, rs = 0 3 nv/ hz crosstalk 11 c t v a = v dd , v b = 0 v 65 db notes 1 1 typicals represent average readings at 25 c and v dd = 5 v. 1 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper 1 positions. r-dnl measures the relative step change from ideal between successive tap positions. see tpc 29 test circuit. 1 i w = 500 a for v dd = 3 v and i w = 2.5 ma for v dd = 5 v for 1 k ? version. 1 3 v ab = v dd , wiper (v w ) = no connect. 1 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. see tpc 28 test circuit. 1 5 resistor terminals a, b, w have no limitations on polarity with respect to each other. 1 6 guaranteed by design and not subject to production test. resistor-terminal capacitance tests are measured with 2.5 v bias on th e measured terminal. the remaining resistor terminals are left open circuit. 1 7 measured at the ax terminals. all ax terminals are open circuited in shutdown mode. 1 8 worst-case supply current consumed when input logic level at 2.4 v, standard characteristic of cmos logic. see tpc 20 for a plot of i dd versus logic voltage. 1 9 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = 5 v. 11 measured at a v w pin where an adjacent v w pin is making a full-scale voltage change. specifications subject to change without notice. electrical characteristics? k version
rev. c C5C AD8400/ad8402/ad8403 specifications (v dd = 3 v 10% or 5 v 10%, v a = v dd , v b = 0 v, ?0 c t a +125 c unless otherwise noted.) dac register load a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 0 1 0 v dd 0v sdi clk cs v out figure 2a. timing diagram 1% error band 1 % t csh t css t dh ax or dx ax or dx t pd_min t pd_max a'x or d'x a'x or d'x 1 0 1 0 1 0 v dd 0v sdi (data in) clk cs v out 1 0 sdo (data out) t ds t ch t cs1 t cl t s t csw figure 2b. detail timing diagram 1% 1% error band rs 1 0 v dd v dd /2 v out t rs t s figure 2c. reset timing diagram electrical characteristics?ll versions parameter symbol conditions min typ 1 max unit switching characteristics 2, 3 input clock pulsewidth t ch , t cl clock level high or low 10 ns data setup time t ds 5ns data hold time t dh 5ns clk to sdo propagation delay 4 t pd r l = 1 k ? to 5 v, c l 20 pf 1 25 ns cs setup time t css 10 ns cs high pulsewidth t csw 10 ns reset pulsewidth t rs 50 ns clk fall to cs rise hold time t csh 0ns cs rise to clock rise setup t cs1 10 ns notes 1 typicals represent average readings at 25 c and v dd = 5 v. 2 guaranteed by design and not subject to production test. resistor-terminal capacitance tests are measured with 2.5 v bias on th e measured terminal. the remaining resistor terminals are left open circuit. 3 see timing diagram for location of measured values. all input control voltages are specified with t r = t f = 1 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. switching characteristics are measured using v dd = 3 v or 5 v. to avoid false clocking, a minimum input logic slew rate of 1 v/ s should be maintained. 4 propagation delay depends on value of v dd , r l , and c l ?ee applications section. specifications subject to change without notice.
rev. c AD8400/ad8402/ad8403 C6C absolute maximum ratings * (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v, +8 v v a , v b , v w to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, v dd a x ?b x , a x ?w x , b x ?w x . . . . . . . . . . . . . . . . . . . . . 20 ma digital input and output voltage to gnd . . . . . . . . 0 v, 7 v operating temperature range . . . . . . . . . . ?0 c to +125 c maximum junction temperature (t j max) . . . . . . . . . . 150 c storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . 300 c package power dissipation . . . . . . . . . . . . . (t j max ?t a )/ ja thermal resistance ( ja ) p-dip (n-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 c/w soic (so-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 c/w p-dip (n-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 c/w p-dip (n-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 c/w soic (so-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 c/w soic (sol-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 c/w tssop-14 (ru-14) . . . . . . . . . . . . . . . . . . . . . . . 180 c/w tssop-24 (ru-24) . . . . . . . . . . . . . . . . . . . . . . . 143 c/w * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table i. serial data word format addr data b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb msb lsb 2 9 2 8 2 7 2 0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8400/ad8402/ad8403 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. c AD8400/ad8402/ad8403 C7C number of number of end-to-end temperature package package devices per branding model channels r ab (k ) range ( c) description option * container information AD8400an10 1 10 ?0 to +125 pdip-8 n-8 50 AD8400a10 AD8400ar10 1 10 ?0 to +125 so-8 so-8 98 AD8400a10 ad8402an10 2 10 ?0 to +125 pdip-14 n-14 25 ad8402a10 ad8402ar10 2 10 ?0 to +125 so-14 so-14 56 ad8402a10 ad8402aru10 2 10 ?0 to +125 tssop-14 ru-14 96 8402a10 ad8402aru10-reel 2 10 ?0 to +125 tssop-14 ru-14 2,500 8402a10 ad8403an10 4 10 ?0 to +125 pdip-24 n-24 15 ad8403a10 ad8403ar10 4 10 ?0 to +125 soic-24 sol-24 31 ad8403a10 ad8403aru10 4 10 ?0 to +125 tssop-24 ru-24 63 8403a10 ad8403aru10-reel 4 10 ?0 to +125 tssop-24 ru-24 2,500 8403a10 AD8400an50 1 50 ?0 to +125 pdip-8 n-8 50 AD8400a50 AD8400ar50 1 50 ?0 to +125 so-8 so-8 98 AD8400a50 ad8402an50 2 50 ?0 to +125 pdip-14 n-14 25 ad8402a50 ad8402ar50 2 50 ?0 to +125 so-14 so-14 56 ad8402a50 ad8402aru50 2 50 ?0 to +125 tssop-14 ru-14 96 8402a50 ad8402aru50-reel 2 50 ?0 to +125 tssop-14 ru-14 2,500 8402a50 ad8403an50 4 50 ?0 to +125 pdip-24 n-24 15 ad8403a50 ad8403ar50 4 50 ?0 to +125 soic-24 sol-24 31 ad8403a50 ad8403aru50 4 50 ?0 to +125 tssop-24 ru-24 63 8403a50 ad8403aru50-reel 4 50 ?0 to +125 tssop-24 ru-24 2,500 8403a50 AD8400an100 1 100 ?0 to +125 pdip-8 n-8 50 AD8400a100 AD8400ar100 1 100 ?0 to +125 so-8 so-8 98 AD8400ac ad8402an100 2 100 ?0 to +125 pdip-14 n-14 25 ad8402a100 ad8402ar100 2 100 ?0 to +125 so-14 so-14 56 ad8402ac ad8402aru100 2 100 ?0 to +125 tssop-14 ru-14 96 8402a-c ad8402aru100-reel 2 100 ?0 to +125 tssop-14 ru-14 2,500 8402a-c ad8403an100 4 100 ?0 to +125 pdip-24 n-24 15 ad8403a100 ad8403ar100 4 100 ?0 to +125 soic-24 sol-24 31 ad8403a100 ad8403aru100 4 100 ?0 to +125 tssop-24 ru-24 63 8403a100 ad8403aru100-reel 4 100 ?0 to +125 tssop-24 ru-24 2,500 8403a100 AD8400an1 1 1 ?0 to +125 pdip-8 n-8 50 AD8400a1 AD8400ar1 1 1 ?0 to +125 so-8 so-8 98 AD8400a1 ad8402an1 2 1 ?0 to +125 pdip-14 n-14 25 ad8402a1 ad8402ar1 2 1 ?0 to +125 so-14 so-14 56 ad8402a1 ad8402aru1 2 1 ?0 to +125 tssop-14 ru-14 96 8402a1 ad8402aru1-reel 2 1 ?0 to +125 tssop-14 ru-14 2,500 8402a1 ad8403an1 4 1 ?0 to +125 pdip-24 n-24 15 ad8403a1 ad8403ar1 4 1 ?0 to +125 soic-24 sol-24 31 ad8403a1 ad8403aru1 4 1 ?0 to +125 tssop-24 ru-24 63 8403a1 ad8403aru1-reel 4 1 ?0 to +125 tssop-24 ru-24 2,500 8403a1 notes * n = plastic dip; so = small outline; ru = thin shrink so the AD8400, ad8402, and ad8403 contain 720 transistors. ordering guide
rev. c AD8400/ad8402/ad8403 C8C AD8400 pin function descriptions pin name description 1 b1 terminal b rdac 2 gnd ground 3 cs chip select input, active low. when cs returns high, data in the serial input register is loaded into the dac register. 4 sdi serial data input 5 clk serial clock input, positive edge triggered. 6v dd positive power supply, specified for operation at both 3 v and 5 v. 7 w1 wiper rdac, addr = 00 2 8 a1 terminal a rdac ad8402 pin function descriptions pin name description 1 agnd analog ground * 2 b2 terminal b rdac #2 3 a2 terminal a rdac #2 4 w2 wiper rdac #2, addr = 01 2 . 5 dgnd digital ground * 6 shdn terminal a open circuit. shutdown controls variable resistors #1 and #2. 7 cs chip select input, active low. when cs returns high, data in the serial input register is decoded based on the address bits and loaded into the target dac register. 8 sdi serial data input 9 clk serial clock input, positive edge triggered. 10 rs active low reset to midscale; sets rdac registers to 80 h . 11 v dd positive power supply, specified for opera tion at both 3 v and 5 v. 12 w1 wiper rdac #1, addr = 00 2 . 13 a1 terminal a rdac #1 14 b1 terminal b rdac #1 * all agnds must be connected to dgnd. ad8403 pin function descriptions pin name description 1 agnd2 analog ground #2 * 2 b2 terminal b rdac #2 3 a2 terminal a rdac #2 4 w2 wiper rdac #2, addr = 01 2 . 5 agnd4 analog ground #4 * 6 b4 terminal b rdac #4 7 a4 terminal a rdac #4 8 w4 wiper rdac #4, addr = 11 2 . 9 dgnd digital ground * 10 shdn active low input. terminal a open circuit. shutdown controls variable resistors #1 through #4. 11 cs chip select input, active low. when cs returns high, data in the serial input register is decoded based on the address bits and loaded into the target dac register. 12 sdi serial data input 13 sdo serial data output, open drain transistor requires pull-up resistor. 14 clk serial clock input, positive edge triggered 15 rs active low reset to midscale; sets rdac registers to 80 h . 16 v dd positive power supply, specified for operation at both 3 v and 5 v. 17 agnd3 analog ground #3 * 18 w3 wiper rdac #3, addr = 10 2 19 a3 terminal a rdac #3 20 b3 terminal b rdac #3 21 agnd1 analog ground #1 * 22 w1 wiper rdac #1, addr = 00 2 23 a1 terminal a rdac #1 24 b1 terminal b rdac #1 * all agnds must be connected to dgnd. pin configurations 1 2 3 4 8 7 6 5 top view (not to scale) AD8400 b1 clk v dd w1 a1 gnd cs sdi 14 13 12 11 10 9 8 1 2 3 4 7 6 5 top view (not to scale) agnd v dd w1 a1 b1 b2 a2 w2 ad8402 sdi clk rs dgnd shdn cs 13 16 15 14 24 23 22 21 20 19 18 17 top view (not to scale) 12 11 10 9 8 1 2 3 4 7 6 5 ad8403 agnd2 agnd1 w1 a1 b1 b2 a2 w2 w3 a3 b3 agnd4 b4 a4 w4 dgnd shdn rs v dd agnd3 cs sdi clk sdo w4
rev. c C9C typical performance characteristics AD8400/ad8402/ad8403 code C decimal 10 8 0 0 32 256 64 96 128 160 192 224 6 4 2 resistance C k v dd = 3v or 5v r ab = 10k r wb r wa tpc 1. wiper to end terminal resistance vs. code wiper resistance C frequency 60 48 0 40.0 42.5 65.0 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 36 24 12 ss = 1205 units v dd = 4.5v t a = 25 c tpc 4. 10 k ? wiper-contact- resistance histogram wiper resistance C frequency 60 48 0 40.0 42.5 65.0 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 36 24 12 ss = 184 units v dd = 4.5v t a = 25 c tpc 7. 100 k ? wiper-contact- resistance histogram i wb current C ma 5 4 0 07 145 3 2 1 23 6 80 h 40 h 20 h ff h code = 10 h t a = 25 c v dd = 5v v wb voltage C v 05 h tpc 2. resistance linearity vs. conduction current digital input code C decimal 1 0.5 C 1 0 32 256 64 96 128 160 192 224 0 C 0.5 inl nonlinearity error C lsb t a = C 40 c t a = +25 c t a = +85 c v dd = 5v tpc 5. potentiometer divider nonlinearity error vs. code temperature C c nominal resistance C k 10 8 0 C 75 C 50 125 C 25 0 25 50 75 100 6 4 2 r ab (end-to-end) r wb (wiper-to-end) code = 80 h r ab = 10k tpc 8. nominal resistance vs. temperature digital input code C decimal 1 0.5 C 1 0 32 256 64 96 128 160 192 224 0 C 0.5 v dd = 5v t a = C 40 c t a = +25 c t a = +85 c r-inl error C lsb tpc 3. resistance step position nonlinearity error vs. code wiper resistance C frequency 60 48 0 35 37 55 39 41 43 45 47 49 51 53 36 24 12 ss = 184 units v dd = 4.5v t a = 25 c tpc 6. 50 k wiper-contact- resistance histogram code C decimal potentiometer mode tempco C ppm/ c 70 60 C 10 0 32 160 64 96 128 30 20 10 0 50 40 192 224 256 v dd = 5v t a = C 40 c/+85 c v a = 2.00v v b = 0v tpc 9. dv wb /dt potentiometer mode tempco
rev. c AD8400/ad8402/ad8403 C10C frequency C hz 6 0 C 54 gain C db 10 1m 100 1k 10k 100k C 6 C 12 C 48 C 18 C 24 C 30 C 36 C 42 code = ff 80 40 20 10 08 04 02 01 t a = +25 c see test circuit 7 tpc 12. 10 k ? gain vs. frequency frequency C hz thd + noise C % 10 0.001 10 100k 100 1k 10k 1 0.1 filter = 22khz v dd = 5v t a = 25 c 0.01 see test circuit 5 see test circuit 6 tpc 15. 50 k ? gain vs. frequency vs. code frequency C hz gain C db 0 C 6 C 48 1k 10k 1m C 30 C 36 C 42 C 12 C 24 C 18 C 54 100k code = ff h 6 80 h 40 h 20 h 10 h 08 h 04 h 02 h 01 h tpc 18. 100 k ? gain vs. frequency vs. code code C decimal 700 600 C 100 0 32 160 64 96 128 300 200 100 0 500 400 192 224 256 rheostat mode tempco C ppm/ c v dd = 5v t a = C 40 c/+85 c v a = no connect r wb measured tpc 10. ? r wb / ? t rheostat mode tempco hours of operation at 150 c 0.75 0.50 C 0.75 0 600 100 300 400 0.25 C 0.25 C 0.50 200 500 code = 80 h v dd = 5v ss = 158 units 0 r wb resistance C % avg + 2 sigma avg avg C 2 sigma tpc 13. long-term drift accelerated by burn-in frequency C hz thd + noise C % 10 0.001 10 100k 100 1k 10k 1 0.1 filter = 22khz v dd = 5v t a = 25 c 0.01 see test circuit 5 see test circuit 6 tpc 16. total harmonic distortion plus noise vs. frequency r w (20mv/div) cs (5v/div) time 500ns/div tpc 11. one position step change at half-scale (code 7f h to 80 h ) output input time 500 tpc 14. large signal settling time v out (50mv/div) time 200ns/div tpc 17. digital feedthrough vs. time
rev. c AD8400/ad8402/ad8403 C11C frequency C hz 10 10k 1m normalized gain flatness C 0.1db/div 100k 100 1k r = 10k see test circuit 7 code = 80 h v dd = 5v t a = 25 c r = 100k r = 50k tpc 19. normalized gain flatness vs. frequency frequency C hz gain C db 0 C 6 1k 10k 1m C 30 C 36 C 42 C 12 C 24 C 18 100k 6 12 f C 3db = 125khz, r = 50k f C 3db = 700khz, r = 10k f C 3db = 71khz, r = 100k v in = 100mv rms v dd = 5v r l = 1m tpc 22. C3 db bandwidths frequency C hz 100k 2m 200k 1m 0 C 10 C 20 0 C 45 C 90 400k 4m 6m phase C degrees 10m gain C db v dd = 5v t a = 25 c wiper set at half-scale 80 h tpc 25. 1 k ? gain and phase vs. frequency digital input voltage C v i dd C supply current C ma 10 1 0.01 05 1234 0.1 t a = 25 c v dd = 5v v dd = 3v tpc 20. supply current vs. digital input voltage frequency C hz 1k 1m 10m 10k 100k i dd C supply current C a 1200 1000 800 600 400 200 0 t a = 25 c a b c d a C b C c C d C v dd = 5.5v code = 55 h v dd = 3.3v code = 55 h v dd = 5.5v code = ff h v dd = 3.3v code = ff h tpc 23. supply current vs. clock frequency i a shutdown current C na 100 1 C 55 C 35 10 v dd = 5v C 15 5 25 45 65 85 105 125 temperature C c tpc 26. shutdown current vs. temperature frequency C hz psrr C db 80 0 100 1m 1k 10k 100k 60 40 v dd = +5v dc 1v p-p ac t a = 25 c code = 80 h c l = 10pf v a = 4v, v b = 0v 20 see test circuit 4 tpc 21. power supply rejection vs. frequency v bias C v r on C 160 0 140 80 60 40 20 120 100 01 6 2345 t a = 25 c v dd = 2.7v v dd = 5.5v see test circuit 3 tpc 24. ad8403 incremental wiper on resistance vs. v dd temperature C c i dd C supply current C a 1 0.1 0.001 C 55 C 35 125 C 155 25456585105 0.01 logic input voltage = 0, v dd v dd = 5.5v v dd = 3.3v tpc 27. supply current vs. temperature
rev. c AD8400/ad8402/ad8403 C12C v+ dut v ms a b w v+ = v dd 1lsb = v+/256 test circuit 1. potentiometer divider nonlinearity error (inl, dnl) dut v ms a b w no connect i w test circuit 2. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) i ms v w2 C [v w1 + i w (r aw ii r bw )] i w v+ v dd where v w1 = v ms when i w = 0 and v w2 = v ms when i w = 1/r v+ dut v ms a b w v w i w = 1v/r nominal r w = CCCCCCCCCCCCCCCCCCCCCCCCCC test circuit 3. wiper resistance psrr (db) = 20log ( CCCCC ) pss (%/%) = CCCCCCC ? v ms ? v dd ? v ms % ? v dd % v+ = v dd 10% v+ v ms a b w v dd v a ~ test circuit 4. power supply sensitivity (pss, psrr) test circuits ab v in 2.5v dc op279 5v v out ~ dut w offset gnd test circuit 5. inverting programmable gain ~ ab v in 2.5v op279 5v v out dut w offset gnd test circuit 6. noninverting programmable gain ~ b a v in 2.5v +15v v out dut w C 15v offset gnd op42 test circuit 7. gain vs. frequency dut i sw b w v bias r sw = 0.1v i sw code = ?? h 0.1v a = nc + C +/ ;!
rev. c AD8400/ad8402/ad8403 C13C operation the AD8400/ad8402/ad8403 provide a single, dual, and quad channel, 256-position digitally controlled variable resistor (vr) device. changing the programmed vr settings is accomplished by clocking in a 10-bit serial data word into the sdi (serial data input) pin. the format of this data word is two address bits, msb first, followed by eight data bits, msb first. table i prov ides the serial register data word format. the AD8400/ad8402/ad 8403 has the following address assignments for the addr decode, which determines the location of vr latch receiving the serial register data in bits b7 through b0: vr a a # =+ + 12 01 (1) the single-channel AD8400 requires a1 = a0 = 0. the dual- channel ad8402 requires a1 = 0. vr settings can be changed one at a time in random sequence. the serial clock running at 10 mhz makes it possible to load all four vrs in under 4 s (10 4 100 ns) for the ad8403. the exact timing requirements are shown in figures 2a, 2b, and 2c. the ad8402/ad8403 resets to midscale by asserting the rs pin, simplifying initial conditions at power up. both parts have a power shutdown shdn pin that places the vr in a zero power consumption state where terminals ax are open circuited and the wiper wx is connected to bx resulting in only leakage cur rents being consumed in the vr structure. in shutdown mode the vr latch settings are maintained so that returning to operational mode from power shutdown, the vr settings return to their previous resistance values. the digital interface is still active in shutdown, except that sdo is deactivated. code changes in the registers can be made that will produce new wiper positions when the device is taken out of shutdown. d7 d6 d5 d4 d3 d2 d1 d0 rdac latch and decoder ax wx bx r s = r nominal /256 r s r s r s r s shdn figure 3. ad8402/ad8403 equivalent vr (rdac) circuit programming the variable resistor rheostat operation the nominal resistance of the vr (rdac) between terminals a and b is available with values of 1 k ? , 10 k ? , 50 k ? , and 100 k ? . the final digits of the part number determine the nominal resistance value, e.g., 10 k ? = 10; 100 k ? = 100. the nominal resistance (r ab ) of the vr has 256 contact points accessed by the wiper terminal, plus the b terminal contact. the 8-bit data word in the rdac latch is decoded to select one of the 256 possible settings. the wiper s first connection starts at the b terminal for data 00 h . this b terminal connection has a wiper contact resistance of 50 ? . the second connection (10 k ? part) is the first tap point located at 89 ? [= r ab (nominal resistance)/256 + r w = 39 ? + 50 ? ] for data 01 h . the third connection is the next tap point representing 78 + 50 = 128 ? for data 02 h . each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,011 ? . the wiper does not directly connect to the b terminal. see figure 3 for a simplified diagram of the equiva- lent rdac circuit. the AD8400 contains one rdac, the ad8402 contains two independent rdacs, and the ad8403 contains four independent rdacs. the general transfer equation that determines the d igi- tally programmed output resistance between wx and bx is: rdx dx r r wb ab w () = () + / 256 (2) where dx is the data contained in the 8-bit rdac# latch, and r ab is the nominal end-to-end resistance. for example, when v b = 0 v and when the a terminal is open circuit, the following output resistance values will be set for the following rdac latch codes (applies to 10 k ? potentiometers): dr wb (dec) ( ) output state 255 10,011 full scale 128 5,050 midscale ( rs = 0 condition) 1891 lsb 0 50 zero-scale (wiper contact resistance) note in the zero-scale condition a finite wiper resistance of 50 ? is present. care should be taken to limit the current flow between w and b in this state to a maximum value of 5 ma to avoid degradation or possible destruction of the internal switch contact. like the mechanical potentiometer the rdac replaces, it is totally symmetrical. the resistance between the wiper w and terminal a also produces a digitally controlled complementary resistance r wa . when these terminals are used, the b terminal can be tied to the wiper or left floating. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the rdac latch is increased in value. the general transfer equation for this operation is: rd d r r wa xx ab w () =? () + 256 256 (3)
rev. c AD8400/ad8402/ad8403 C14C where dx is the data contained in the 8-bit rdac# latch, and r ab is the nominal end-to-end resistance. for example, when v a = 0 v and b terminal is open circuit, the following output resistance values will be set for the following rdac latch codes (applies to 10 k ? potentiometers): dr wa (dec) ( ) output state 255 89 full-scale 128 5,050 midscale ( rs = 0 condition) 1 10,011 1 lsb 0 10,050 zero-scale the typical distribution of r ab from channel to channel matches within 1%. however, device-to-device matching is process lot- dependent, having a 20% variation. the change in r ab with temperature has a positive 500 ppm/ c temperature coefficient. the wiper-to-end-terminal resistance temperature coefficient has the best performance over the 10% to 100% of adjustment range where the internal wiper contact switches do not contribute any significant temperature related errors. the graph in tpc 10 shows the performance of r wb tempco versus code. using the trimmer with codes below 32 results in the larger temperature coefficients plotted. programming the potentiometer divider voltage output operation the digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. for example, connecting a terminal to 5 v and b terminal to ground produces an output voltage at the wiper starting at zero volts up to 1 lsb less than 5 v. each lsb of voltage is equal to the voltage applied across terminal ab divided by the 256 position resolution of the potentiometer divider. the general equation defining the output voltage with respect to ground for any given input voltage applied to terminals ab is: vd d v v w xx ab b () =+ 256 (4) operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. here the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the temperature drift improves to 15 ppm/ c. at the lower wiper position settings, the potentiometer divider temperature coefficient increases due to the contributions of the cmos switch wiper resistance becoming an appreciable portion of the total resistance from terminal b to the wiper. see tpc 9 for a plot of potentiometer tempco performance versus code setting. digital interfacing the AD8400/ad8402/ad8403 contain a standard spi compat- ible three-wire serial input control interface. the three inputs are clock (clk), cs and serial data input (sdi). the positive- edge sensitive clk input requires clean transitions to avoid clocking incorrect data into the serial input register. for best results use logic transitions faster than 1 v/ s. standard logic families work well. if mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. the figure 4 block diagrams show more detail of the internal digital circuitry. when cs is taken active low, the clock loads data into the 10-bit serial register on each positive clock edge (see table ii). rdac latch #1 gnd a1 w1 b1 v dd AD8400 cs clk 8 d7 d0 en addr dec a1 a0 sdi di ser reg d0 d7 10-bit a. rdac latch #1 r agnd rs a1 w1 b1 v dd ad8402 cs clk d7 d0 rdac latch #2 r a4 w4 b4 d7 d0 en addr dec a1 a0 sdi di 10-bit ser reg d0 shdn dgnd d7 8 b. rdac latch #1 r agnd rs a1 w1 b1 v dd ad8403 cs clk sdo d7 d0 rdac latch #4 r a4 w4 b4 d7 d0 en addr dec a1 a0 d7 sdi do di ser reg d0 shdn dgnd 8 c. figure 4. block diagrams
rev. c AD8400/ad8402/ad8403 C15C table ii. input logic control truth table clk cs rs shdn register activity l l h h no sr effect, enables sdo pin. p l h h shift one bit in from the sdi pin. the tenth previously entered bit is shifted out of the sdo pin. x p h h load sr data into rdac latch based on a1, a0 decode (t able iii). x h h h no operation x x l h sets all rdac latches to midscale, wiper centered, and sdo latch cleared. x h p h latches all rdac latches to 80 h . x h h l open circuits all resistor a-terminals, connects w to b, turns off sdo output transistor. note p = positive edge, x = don t care, sr = shift register. the serial data-output (sdo) pin contains an open drain n-channel fet. this output requires a pull-up resistor in order to transfer data to the next package s sdi pin. the pull-up resistor termination voltage may be larger than the v dd supply (but less than max v dd of 8 v) of the ad8403 sdo output device, e.g., the ad 8403 could operate at v dd = 3.3 v and the pull-up for interface to the next device could be set at 5 v. this allows for daisy-chaining several rdacs from a single processor serial data line. the clock period needs to be increased when using a pull-up resistor to the sdi pin of the following device in the series. capacitive loading at the daisy-chain node sdo sdi between devices must be accounted for to successfully transfer data. when daisy chaining is used, the cs should be kept low until all the bits of every package are clocked into their respective serial registers ensuring that the address bits and data bits are in the proper decoding location. this would require 20 bits of address and data complying to the word format provided in table i if two ad8403 four-channel rdacs are daisy-chained. note, only the ad8403 has a sdo pin. during shutdown shdn the sdo output pin is forced to the off (logic high) state to d isable power dissipation in the pull-up resistor. see figure 6 for equivalent sdo output circuit schematic. the data setup and data hold times in the specification table determine the data valid time requirements. the last 10 bits of the data word entered into the serial register are held when cs returns high. at the same time cs goes high it gates the address decoder, which enables one of the two (ad8402) or four (ad8403) positive edge triggered rdac latches. see figure 5 detail and table iii address decode table. table iii. address decode table a1 a0 latch decoded 0 0 rdac#1 0 1 rdac#2 1 0 rdac#3 ad8403 only 1 1 rdac#4 ad8403 only addr decode rdac 1 rdac 2 rdac 4 serial register ad8403 sdi clk cs figure 5. equivalent input control logic the target rdac latch is loaded with the last eight bits of the serial data word completing one dac update. in the case of the ad8403 four separate 10-bit data words must be clocked in to change all four vr settings. serial register sdi ck rs dq shdn cs clk rs sdo figure 6. detail sdo output schematic of the ad8403 all digital pins are protected with a series input resistor and parallel zener esd structure shown in figure 7a. this structure applies to digital pins cs , sdi, sdo, rs , shdn , clk. the digital input esd protection allows for mixed power supply applications where 5 v cmos logic can be used to drive an AD8400, ad8402, or ad8403 operating from a 3 v power sup- ply. the analog pins a, b, and w are protected with a 20 ? series resistor and parallel zener (see figure 7b). 1k digital pins logic figure 7a. equivalent esd protection circuits 20 a, b, w ". :61 <1= c w 120pf ab c a c b w c a = 90.4pf (dw / 256) + 30pf rdac 10k c b = 90.4pf [1 C (dw / 256)] + 30pf "/ 68 a#2 3 ?
rev. c AD8400/ad8402/ad8403 C16C the ac characteristics of the rdacs are dominated by the internal parasitic capacitances and the external capacitive loads. the 3db bandwidth of the ad8403an10 (10 k ? resistor) measures 600 khz at half scale as a potentiometer divider. tpc 22 provides the large signal bode plot characteristics of the three available resistor versions 10 k ? , 50 k ? , and 100 k ? . the gain flatness versus frequency graph, tpc 25, predicts filter applications perform ance. a parasitic simulation model has been developed, and is shown in figure 8. listing i provides a macro model net list for the 10 k ? rdac: listing i. macro model net list for rdac .param dw=255, rdac=10e3 * .subckt dpot (a,w,) * ca a 0 {dw/256*90.4e-12+30e-12} raw a w {(1-dw/256)*rdac+50} cw w 0 120e-12 rbw w b {dw/256*rdac+50} cb b 0 {(1-dw/256)*90.4e-12+30e-12} * .ends dpot the total harmonic distortion plus noise (thd+n) is measured at 0.003% in an inverting op amp circuit using an offset ground and a rail-to-rail op279 amplifier, test circuit 5. thermal noise is primarily johnson noise, typically 9 nv/ hz for the 10 k ? version at f = 1 khz. for the 100 k ? device, thermal noise becomes 29 nv/ hz . channel-to-channel crosstalk measures less than 65 db at f = 100 khz. to achieve this isolation, the extra ground pins provided on the package to segregate the individual rdacs must be connected to circuit ground. agnd and dgnd pins should be at the same voltage potential. any unused potentio- meters in a package should be connected to ground. power supply rejection is typically 35 db at 10 khz. care is needed to minimize power supply ripple in high accuracy applications. applications the digital potentiometer (rdac) allows many of the applications of trimming potentiometers to be replaced by a solid-state solu- tion offering compact size and freedom from vibration, shock and open contact problems encountered in hostile environ ments. a major advan tage of the digital potentiometer is its programma- bility. any settings can be saved for later recall in system memory. the two major configurations of the rdac include the potentiometer divider (basic 3-terminal application) and the rheostat (2-terminal configuration) connections shown in test circuits 1 and 2 (see page 11). certain boundary conditions must be satisfied for proper ad 8400/ ad8402/ad8403 operation. first, all analog signals must remain within the 0 to v dd range used to operate the single-supply AD8400/ad8402/ad8403 products. for standard potentiometer divider applications, the wiper output can be used directly. for low resistance loads, buffer the wiper with a suitable rail-to-rail op amp such as the op291 or the op279. second, for ac signals and bipolar dc adjustment applications, a virtual ground will generally be needed. whatever method is used to create the virtual ground, the result must provide the necessary sink and source current for all connected loads, including adequate bypass capacitance. test circuit 5 (see page 11) shows one channel of the ad8402 connected in an inverting programmable gain amplifier circuit. the virtual ground is set at 2.5 v, which allows the circuit output to span a 2.5 volt range with respect to virtual ground. the rail-to-rail amplifier capability is necessary for the widest output swing. as the wiper is adjusted from its midscale reset position (80 h ) toward the a terminal (code ff h ), the voltage gain of the circuit is increased in successfully larger increments. alternatively, as the wiper is adjusted toward the b terminal (code 00 h ), the signal becomes attenuated. the plot in figure 9 shows the wiper settings for a 100:1 range of voltage gain (v/v). note the 10 db of pseudo-logarithmic gain around 0 db (1 v/v). this circuit is mainly useful for gain adjustments in the range of 0.14 v/v to 4 v/v; beyond this range the step sizes become very large and the resistance of the driving circuit can become a significant term in the gain equation. inverting gain C v/v 256 128 0 0.1 1.0 10 96 64 32 160 192 224 digital code C decimal figure 9. inverting programmable gain plot
rev. c AD8400/ad8402/ad8403 C17C active filter one of the standard circuits used to generate a low-pass, high- pass, or band-pass filter is the state variable active filter. the digital potentiometer allows full programmability of the frequency, gain and q of the filter outputs. figure 10 shows the filter circuit using a 2.5 v virtual ground, which allows a 2.5 v p input and output swing. rdac2 and 3 set the lp, hp, and bp cutoff and center frequencies, respectively. these variable resistors should be programmed with the same data (as with ganged potentiom- eters) to maintain the best circuit q. figure 11 shows the measured filter response at the band-pass output as a function of the rdac2 and rdac3 settings which produce a range of center frequencies from 2 khz to 20 khz. the filter gain response at the band-pass output is shown in figure 12. at a center frequency of 2 khz, the gain is adjusted over a 20 db to +20 db range determined by rdac1. circuit q is adjusted by rdac4. for more detailed reading on the state variable active filter, see analog devices application note, an-318. a1 rdac1 v in b a2 a3 a4 rdac4 b 10k 10k op279 2 rdac2 rdac3 b b 0.01 f 0.01 f band- pass high- pass low- pass figure 10. programmable state variable active filter frequency C hz 40 20 C 80 20 100k 100 1k 10k 0 C 20 C 40 C 60 200k amplitude C db C 0.16 20.0000 k a figure 11. programmed center frequency band-pass response frequency C hz 40 20 C 80 20 100k 100 1k 10k 0 C 20 C 40 C 60 200k amplitude C db C 19.01 2.00000 k a figure 12. programmed amplitude band-pass response
rev. c AD8400/ad8402/ad8403 C18C outline dimensions dimensions shown in inches and (mm). 8-lead plastic dip (n-8) seating plane 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) min 8 14 5 pin 1 0.280 (7.11) 0.240 (6.10) 0.100 (2.54) bsc 0.430 (10.92) 0.348 (8.84) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) 8-lead soic (r-8) 0.1968 (5.00) 0.1890 (4.80) 85 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 14-lead plastic dip package (n-14) 14 1 7 8 pin 1 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) 0.100 (2.54) bsc seating plane 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) min 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62)
rev. c AD8400/ad8402/ad8403 C19C 14-lead narrow body soic package (so-14) 14 8 7 1 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 0.3444 (8.75) 0.3367 (8.55) 0.050 (1.27) bsc seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 0.0500 (1.27) 0.0160 (0.41) 0.0099 (0.25) 0.0075 (0.19) 14-lead tssop (ru-14) 14 8 7 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 24-lead narrow body plastic dip package (n-24) 24 112 13 pin 1 1.275 (32.30) 1.125 (28.60) 0.280 (7.11) 0.240 (6.10) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) seating plane 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.200 (5.05) 0.125 (3.18) 0.150 (3.81) min 0.100 (2.54) bsc 0.070 (1.77) 0.045 (1.15)
rev. c C20C c01092C0C2/02(c) printed in u.s.a. AD8400/ad8402/ad8403 outline dimensions (continued) dimensions shown in inches and (mm). 24-lead soic package (sol-24) 0.0125 (0.32) 0.0091 (0.23) 8 0 0.0291 (0.74) 0.0098 (0.25) 45 0.0500 (1.27) 0.0157 (0.40) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 24 13 12 1 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 0.6141 (15.60) 0.5985 (15.20) 24-lead thin surface-mount tssop package (ru-24) 24 13 12 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.311 (7.90) 0.303 (7.70) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 revision history location page data sheet changed from rev. b to rev. c. addition of new figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 edits to tpcs 1, 8, 12, 16, 20, 24, 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 edits to programming the variable resistor section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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